As dynamic random access memory (DRAM) devices scale to smaller dimensions, an increasing emphasis is placed on patterning for forming three dimensional structures, including trenches for storage nodes as well as access transistors. In present day DRAM devices, transistors may be formed using narrow and tall semiconductor fin structures, often made from monocrystalline silicon. In accordance with predicted trends, the aspect ratio of such fin structures, meaning the height (depth) of a fin divided by the spacing between adjacent fins, may reach 20:1 or more in the coming years. Moreover, the absolute dimensions of such fin structures within the plane of a substrate are so small wherein the fin structures are not readily patternable using known deep ultraviolet lithography tools.
With respect to these and other considerations, the present disclosure is provided.